This disclosure relates generally to integrated circuit structures, and more particularly to forming interconnect structures for integrated circuits using pre-ink-printed sheets.
Among the efforts for reducing the size of integrated circuits and reducing RC delay, three-dimensional integrated circuits (3DICs) and stacked dies are commonly used. Through-silicon vias (TSVs) are thus used in 3DICs and stacked dies. In this case, TSVs are often used to connect the integrated circuits on a die to the backside of the die. In addition, TSVs are also used to provide short grounding paths for grounding the integrated circuits through the backside of the die, which may be covered by a grounded metallic film.
TSV connections often require redistribution lines to be formed on the backside of wafers and connected to TSVs. Conventional backside TSV interconnections were formed using processes, such as chemical vapor deposition (CVD) methods, physical vapor deposition (PVD) methods, lithography processes, etching processes, and/or the like. These methods involve high costs. Further, these methods often require elevated temperatures of wafers, typically 200 to 400 degrees centigrade. Accordingly, thermally-induced stresses were introduced into the resulting wafers and chips and caused warpage of the wafers/chips. Furthermore, breaking of the dielectric layers and delamination between the dielectric layers in the wafers/chips may also occur.